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100 Evaluating the use of single-wafer wet cleans with organic spin-on dielectric materials
Author(s): L. Archer (Affiliation: SEZ, Phoenix, AZ, USA), M. Simmonds, F. Tolic, J. Waeterloos
Journal: Micro (USA), vol.22, no.5, p.103-8 (June 2004)
Publisher: Canon Communications, USA
Language: English
ISSN: 1081-0595
Document type: Journal article
Abstract: The purpose of the study described in this article was to evaluate the impact of a single-wafer postetch cleaning tool on porous SiLK dielectric resin films manufactured by Dow Chemical (Midland, MI). The article focuses on the relationship between different chemical process approaches and the resulting electrical characteristics of cleaned structures. The electrical test characterization results presented here show that a single-wafer cleaning step, depending on the particular chemistry formulation used, can improve the performance of selected test devices by lowering line resistance (R) and increasing capacitance (C). The data show that an appropriate chemical clean can result in electrical RC product performance that is as good as or better than that of the non-wet-clean process of record (POR)
Inspec No.: 8248204
101 Using a tungsten plasma clean process to reduce metal shorts caused by CMP microscratches
Author(s): H. Ollendorf, S. Cabral, R. Fuller (Affiliation: Infineon Technol., Richmond, VA, USA)
Journal: Micro (USA), vol.22, no.6, p.57-63 (July 2004)
Publisher: Canon Communications, USA
Language: English
ISSN: 1081-0595
Document type: Journal article
Abstract: A common problem associated with the chemicalmechanical planarization (CMP) processes used in damascene sequences is the generation of microscratches. Microscratches form small trenches in the oxide, which are filled with tungsten during CMP processing. These metal-filled trenches, in turn, can short the intended patterned circuitry. In tests performed at Infineon Technologies' wafer fab in Richmond, VA, engineers determined that by introducing a dry plasma clean after the tungsten CMP process, the yield impact of microscratches can be reduced or eliminated. They discovered that the plasma etch process removes tungsten uniformly both from the intended metal pattern and the unintended metal residue in the trench caused by the scratch. The metal short can be eliminated by adjusting the etch depth to the actual scratch depth (2 refs.)
Inspec No.: 8248205
102 Using an ICP-based strip system to perform resist and barrier-layer removal in copper low-k processes
Author(s): S. Savas, R. George, D. Gilbert (Affiliation: Mattson Technol., Freemont, CA, USA), J. Cain, M. Herrick, A. Nagy, K. Karuppana
Journal: Micro (USA), vol.22, no.8, p.61-70 (Oct.-Nov. 2004)
Publisher: Canon Communications, USA
Language: English
ISSN: 1081-0595
Document type: Journal article
Abstract: The successful integration of copper interconnects and low-k dielectrics in dual-damascene processes has been a critical and difficult step in the development of IC technology. One part of the copper/low-k integration process, stripping photoresist and cleaning wafers without damaging the low-k materials, has been a significant challenge (Louis et al., 2001; Gao et al., 1999). This article demonstrates the use of an electrostatic-shielded inductively coupled plasma (ICP) and radio-frequency (RF)-biased stripping system that was installed at Freescale Semiconductor's Austin, TX, facility to strip photoresist and remove the barrier layer covering the copper lines. In this two-in-one scheme, dielectric etch is performed in an etch tool, after which resist strip and residue removal steps followed by barrier-layer removal are performed in an Aspen III Highlands ICP-based strip tool from Mattson (Fremont, CA). The two-in-one approach was compared with the process of record (POR), in which low-k etch and barrierlayer-removal steps were performed in the etch tool (9 refs.)
Inspec No.: 8248206
103 Formation of ultrathin oxide layers by low temperature oxidation in RF plasma
Author(s): T. Bieniek, R.B. Beck, R. Jakubowski (Affiliation: Instytut Mikroelektroniki i Optoelektroniki, Politechnika Warszawska, Warsaw, Poland ), A. Kudla
Journal: Elektronika (Poland), vol.45, no.10, p.6-7 (2004)
Publisher: SIGMA NOT, Poland
Language: Polish
ISSN: 0033-2089
Document type: Journal article
Abstract: The aim of this work is the experimental study of potential possibilities of oxidation in RF. (13, 56 MHz) plasma application for the formation of ultra-thin (<10 nm) oxide layers (1 refs.)
Inspec No.: 8248401
104 Process optimization and PFC emission reduction using a c-C4 F8 chamber cleaning process on a novellus concept 1 dielectric PECVD tool
Author(s): E.M. Chan (Affiliation: NEC Electron. America, Roseville, CA, USA), G. Loh, C.C. Allgood
Journal: IEEE Trans. Semicond. Manuf. (USA), vol.17, no.4, p.497-503 (Nov. 2004)
Publisher: IEEE, USA
Language: English
ISSN: 0894-6507, Full text
Document type: Journal article
Abstract: While the new generation of chemical vapor deposition (CVD) tools adapts NF3 as a chamber clean gas to reduce perfluorocompound (PFC) reductions, process optimization (C2F6) and alternative CxFy clean chemistries are options for the installed-base tools. From a previous study comparing the various C xFy chamber clean chemistries, we further conducted a production test in a 150-mm wafer fabrication facility comparing the best alternative CxFy clean chemistry (C4F8 clean) with an optimized C2 F6 clean process on a Novellus Concept 1 Dielectric tool running TEOS-based SiO2 CVD. Gas flow rates, chamber pressure, and oxygen volume percentages were studied as variables to develop an optimal c-C4F8 process recipe for maintaining or improving cleaning efficiency while reducing gas consumption and PFC emissions compared to the optimized C2F 6 process. After the initial experimental matrix was completed, several singlevariable experiments were run to fine tune the recipe. Based on the data analysis and the model results from the design of experiment, two optimal C4F8 cleaning processes were identified. Both processes significantly lowered gas consumption and PFC emissions. Marathon process testing showed no adverse impact on film properties or device yield (7 refs.)
Inspec No.: 8251709
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