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117 Abnormal contact resistance reduction of bonded copper interconnects in three-dimensional integration during current stressing
Author(s): K.N. Chen, C.S. Tan, A. Fan, R. Reif (Affiliation: Microsystems Technol. Labs., Massachusetts Inst. of Technol., Cambridge, MA, USA)
Journal: Appl. Phys. Lett. (USA), vol.86, no.1, p.11903-1-3 (3 Jan. 2005)
Publisher: AIP, USA
Language: English
ISSN: 0003-6951, Full text
Document type: Journal article
Abstract: Bonded copper interconnects were stressed withcurrent to measure the specific contact resistance. For bondedcopper interconnects without a prebonding HCl clean, thecorresponding specific contact resistance did not change whileincreasing the stress current. However, for someinterconnects with the prebonding HCl clean, an abnormalcontact resistance reduction was observed during the increaseof the stress current. The rise of temperature at the bondinginterface area due to Joule heating under high current densitymay have caused the decrease of contact resistance. Thisbehavior may be one option for quality enhancement in 3Dintegration at low temperature (8 refs.)
Inspec No.: 8247066
118 A novel electroplanarization system for replacement of CMP
Author(s): J. Huo, R. Solanki (Affiliation: OGI Sch. of Sci. & Eng., Beaverton, OR, USA), J. McAndrew
Journal: Electrochem. Solid-State Lett. (USA), vol.8, no.2, p.C33-5 (Feb. 2005)
Publisher: Electrochem. Soc, USA
Language: English
ISSN: 1099-0062, Full text
Document type: Journal article
Abstract: A novel design of electrochemical planarization(ECP) system is proposed consisting of a rotating anode, asegmented cathode with very small interelectrode distance,and forced convection. Copper and tantalum anodicpolarization curves and steady-state data were collected tovalidate the electropolishing conditions of the new design.Excellent ECP was produced on patterned electroplatedcopper films on silicon wafers using this approach (11 refs.)
Inspec No.: 8249222
119 Novel advanced interconnects
Author(s): R. Labennett, A. Huffman (Affiliation: Opt. & Electron. Packaging Group, MCNC-RDI, USA)
Journal: Adv. Packag. (USA), vol.13, no.10, p.35-7 (Oct. 2004)
Publisher: PennWell Publishing, USA
Language: English
ISSN: 1065-0555
Document type: Journal article
Abstract: Solder interconnects have been supplied for anumber of years by captive manufacturers for PCs and forautomotive applications. Contract wafer bump bondingmanufacturers are providing reliable standard-pitchinterconnects at low cost, while microelectronics materialssuppliers continue to make leaping advances in the materialsfor these interconnect technologies. Advances in commerciallyavailable specialty materials for microelectronics have resultedin denser solder interconnects and more robust processes.Demanding applications, such as high-performance imagingarrays requiring thinned wafers, may push the fine-pitchinterconnect supply chain out of the processing comfort zone.Researchers at MCNC's Research and Development Institute(MCNC-RDI), a North Carolina-based nonprofit researchorganization, address these demanding requirements throughthe deployment of materials and novel designs to meettomorrow's fine-pitch interconnection needs. This articlereports on some fine-pitch solder interconnect solutions thatresulted from the simultaneous deployment of these advancedmaterials, unique interconnect designs and assemblytechniques (4 refs.)
Inspec No.: 8248649
120 Inter-LSI-chips interconnection technology using ultrasonic bonding method
Author(s): T. Miyazaki (Affiliation: Packaging Eng. Div., NEC Electron. Corp., Sagamihara, Japan), Y. Kurita, T. Kimura, R. Yoshino, K. Oyachi
Journal: Trans. Inst. Electron. Inf. Commun. Eng. C (Japan), vol.J87-C, no.11, p.820-7 (Nov. 2004)
Publisher: Inst. Electron. Inf. & Commun. Eng, Japan
Language: Japanese
ISSN: 1345-2827
Document type: Journal article
Abstract: COC (chip on chip) interconnection technology for3D integrated semiconductor devices had developed. Wehave proposed and developed an on-chip system integrationtechnology based on a new chip-on-chip interconnectionprocess using adhesive resin layer formed chip and ultrasonicflip chip bonding technology. We had evaluated this newprocess by QFP Package and examined basis reliability tests.As a result, the possibility of realization has been confirmed.We had analyzed the QFP Package by observations of crossand plane section grinding and EDX analysis. Therefore, theinterconnection mechanism at this new process that Au studbumps pierce the adhesive resin layer and interconnect to Alpads has estimated (7 refs.)
Inspec No.: 8251403
121 A survey of mesh-based power/ground network analysis
Author(s): Yan Wen-Fang, Li Chun-Qiang, Ma Qi, Yan Xiao-Lang (Affiliation: IC-CAD Center, Hangzhou Inst. of Electron. Eng., China)
Journal: Microelectron. (China), vol.34, no.4, p.460-5 (Aug. 2004)
Publisher: Editorial Dept. Microelectronics, China
Language: Chinese
ISSN: 1004-3365
Document type: Journal article
Abstract: In deep sub-micron VLSI, it is very critical to analyzepower/ground networks efficiently during the design, in orderto obtain a robust design. According to mathematical model ofmesh-based power/ground network analysis, latestprogresses in the research and development of power/groundnetwork analysis are described and problems related arediscussed (12 refs.)
Inspec No.: 8251495
122 Wide-band modelling of CMOS interconnections and damages with the lumped element LE-FDTD method
Author(s): F. Alimenti, A. Scorzoni, L. Roselli (Affiliation: DIEI, Perugia Univ., Italy ), M. Impronta
Journal: Int. J. Numer. Model., Electron. Netw. Devices Fields (UK), vol.17, no.6, p.561-73 (Nov.-Dec. 2004)
Publisher: Wiley, UK
Language: English
ISSN: 0894-3370, Full text
Document type: Journal article
Abstract: This paper illustrates the application of a lumpedelement-finite difference time domain (LE-FDTD) simulator tothe wide-band modelling of CMOS interconnections. Toachieve very accurate results the short-open calibration (SOC)technique has been adopted. Specific parameters of a CMOSinterconnection laterally screened by a stack of metal viashave been extracted in the two cases of an unperturbed and apurposely damaged metal line. The behaviour of void-likedefects in the metal line has been also studied using the fullythree-dimensional capabilities of the simulator. It has beendemonstrated that, at least in the simulated cases, only thespecific resistance is affected by damaging (23 refs.)
Inspec No.: 8251609
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