|
123 Stability and electronic properties of carbon nanotubes adsorbed on Si(001)
Author(s): W. Orellana (Affiliation: Inst. de Fisica, Sao Paulo Univ., Brazil), R.H. Miwa, A. Fazzio
Conference: 22nd European Conference on Surface Science, Prague, Czech Republic
Conference Date: 7-12 Sept. 2003
Journal: Surf. Sci. (Netherlands), vol.566-568, pt.2, p.728-32 (20 Sept. 2004)
Publisher: Elsevier, Netherlands
Language: English
ISSN: 0039-6028, Full text
Document type: Conference paper in journal
Abstract: We report first-principles calculations on theadsorption of an armchair (6,6) single-walled carbon nanotube(CNT) on the Si(001) surface. We study several well-orderedadsorption configurations for the nanotube on the Si surface.Our results show stable geometries between two consecutiveSi-dimer rows (the surface trench). The binding energy pertube length for the CNT in the most stable geometry iscalculated to be 0.2 eV/â. In this geometry, we observe theformation of C-Si chemical bonds. The density of states alongthe dimer rows for the lowest-energy adsorbed configurationshows an increase in the number of states at the Fermi level.This suggests an enhancement of the nanotube metalliccharacter throughout the contact with the Si surface due to theformation of the C-Si bonds. These properties may lead toconsider metallic CNTs as one-dimensional wires on thesilicon surface with promising applications for contact andinterconnections of future nanoscale electronic devices (14refs.)
Inspec No.: 8253035
124 150 ìm pitch flipchip packaging with Pb-free solder and Cu/low-k interconnects
Author(s): Seung Wook Yoon, Vaidyanathan Kripesh, Li Hong Yu, M.K. Iyer (Affiliation: Inst. of Microelectron., Singapore, Singapore)
Editor(s): K.C.Toh, Y.C.Mui, J.How, J.H.L.Pang
Conference: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004), Singapore
Conference Date: 8-10 Dec. 2004
Publication: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)
Publisher: IEEE, USA, 2004
Language: English
ISBN: 0 7803 8821 6 Page: 126-31
Document type: Conference paper
Abstract: In this paper, low-k test vehicles with four Cu layersare fabricated using Cu dual damascene process. Polymerencapsulation and metal redistribution is applied using waferintegration technology to minimize the stress from the solderbump pad to low-k ILD (interlayer dielectric). Two differentinterconnections were studied; i) Pb-free solder bump and ii)copper column. Ti/NiV/Cu/Au UBM is deposited on the Cu/low-k wafers and Sn-4.0Ag-0.5Cu Pb-free solder are bumpedfor solder interconnection. For copper column interconnection,thick PR process is developed and optimized for electro Cuplating and solder is deposited on the top of Cu post. Bumpshear test is carried out to evaluate the bump bonding andanalyzed the failure. In order to investigate UBM and solderjoint reliability, multiple reflows were carried out.Microstructure observation and failure analysis wereperformed and observed with optical and electron microscopy.The paper will also present the reliability and failure analysisstudies carried out in characterizing the UBM structures (5refs.)
Inspec No.: 8256057
125 Ultra fine-pitch wafer level packaging with reworkable composite nano-interconnects
Author(s): A.O. Aggarwal, P. Markondeya Raj (Affiliation: Microsystems Packaging Res. Center, Georgia Inst. of Technol., Atlanta, Germany), M.D. Sacks, A.A.O. Tay, R.R. Tummala
Editor(s): K.C.Toh, Y.C.Mui, J.How, J.H.L.Pang
Conference: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004), Singapore
Conference Date: 8-10 Dec. 2004
Publication: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)
Publisher: IEEE, USA, 2004
Language: English
ISBN: 0 7803 8821 6 Page: 132-7
Document type: Conference paper
Abstract: The decrease in feature sizes of micro-electronicdevices has underlined the need for higher number of I/O's inorder to increase its functionality. This has spurred a greatinterest in developing electronic packages with fine and ultrafine pitches (20-100 microns). Most of the compliantinterconnects that are currently being developed haveinductance and resistance higher than desirable. This paperpresents a novel low-temperature fabrication process thatcombines polymer structures with electroless copper plating tocreate low stress MEMS structures for extremely fine pitchwafer level packages. Finite element analysis of thesestructures shows tremendous reduction in the stresses at theinterfaces and superior reliability as IC-package nanointerconnects. Low CTE polyimide structures with ultra-lowstress, high toughness and strength were fabricated usingplasma etching. This dry etching process was tuned to yield awall angle above 80 degrees. The etching process also leadsto roughened sidewalls for selective electroless copper platingon the sidewalls of polymer structures. Metal-coated polymerstructures from MEMS fabrication techniques can provide lowcosthigh-performance solutions for wafer-level-packaging.This work also describes a material solution synthesis route todevelop reworkable nano-dimensional interfaces for ICpackagebonding. Reworkability is addressed by a thin (200nm) interface of lead-free high-strength solders using selectiveelectroless plating. Lead-free alloy films were deposited fromaqueous plating solutions consisting of suitable metal saltsand reducing agents at 45°C. The lead-free soldercomposition was controlled by altering the plating bathformulation and was characterized using SEM, XRD and XPS.Solder film formed from the above approach wasdemonstrated to bond the metal-coated polymer interconnectswith the copper pads on the substrate (9 refs.)
Inspec No.: 8256058
|
