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165 Two-dimensional analytical threshold voltage model for DMG Epi-MOSFET
Author(s): K. Goel (Affiliation: Dept. of Electron. Sci., Univ. of Delhi, New Delhi, India), M. Saxena, M. Gupta, R.S. Gupta
Journal: IEEE Trans. Electron Devices (USA), vol.52, no.1, p.23-9 (Jan. 2005)
Publisher: IEEE, USA
Language: English
ISSN: 0018-9383, Full text
Document type: Journal article
Abstract: A two-dimensional (2-D) analytical model of a dualmaterial gate (DMG) epitaxial (Epi)-MOSFET for improved,SCEs, hot electron effects, and carrier transport efficiency ispresented. Using a two-region polynomial potential distributionand a universal boundary condition, we calculated the 2-Dpotential and electric field distribution along the channel. Anexpression for threshold voltage for short-channel DMG Epi-MOSFETs is also derived. The ratio of gate lengths has beenvaried to show which gate length ratio gives the bestperformance. The analytical results have been validated bythe 2-D device simulator ATLAS over a wide range of deviceparameters and bias conditions (17 refs.)
Inspec No.: 8249839
166 Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs
Author(s): Yi-Ming Sheu, Sheng-Jier Yang, Chih-Chiang Wang, Chih-Sheng Chang, Li-Ping Huang, Tsung-Yi Huang (Affiliation: Dept. of Adv. Device Technol., Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan), Ming-Jer Chen, C.H. Diaz
Journal: IEEE Trans. Electron Devices (USA), vol.52, no.1, p.30-8 (Jan. 2005)
Publisher: IEEE, USA
Language: English
ISSN: 0018-9383, Full text
Document type: Journal article
Abstract: The effect of shallow trench isolation mechanicalstress on MOSFET dopant diffusion has become significant,and affects device behavior for sub-100-nm technologies. Thispaper presents a stress-dependent dopant diffusion modeland demonstrates its capability to reflect experimental resultsfor a state-of-the-art logic CMOS technology. The proposedstress-dependent dopant diffusion model is shown tosuccessfully reproduce device characteristics covering a widerange of active area sizes, gate lengths, and device operatingconditions (21 refs.)
Inspec No.: 8249840
167 Threshold voltage control in NiSi-gated MOSFETs through SIIS
Author(s): J. Kedzierski (Affiliation: IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA), D. Boyd, C. Cabral, P. Ronsheim, S. Zafar, P.M. Kozlowski, J.A. Ott, Meikei Ieong
Journal: IEEE Trans. Electron Devices (USA), vol.52, no.1, p.39-46 (Jan. 2005)
Publisher: IEEE, USA
Language: English
ISSN: 0018-9383, Full text
Document type: Journal article
Abstract: Complete gate silicidation has recently beendemonstrated as an excellent technique for the integration ofmetal gates into MOSFETs. From the various silicide gatematerials NiSi has been shown to be the most scalable. In thispaper, a versatile method for controlling the workfunction of anNiSi gate is presented. This method relies on doping the poly-Si with various impurities prior to silicidation. The effect ofvarious impurities including B, P, As, Sb, In, and Al isdescribed. The segregation of the impurities from the poly-Sito the silicide interface during the silicidation step is found tocause the NiSi workfunction shift. The effect of the segregatedimpurities on gate capacitance, mobility, local workfunctionstability, and adhesion is studied (12 refs.)
Inspec No.: 8249841
168 Simulated operation and properties of sourcegated thin-film transistors
Author(s): T. Lindner, G. Paasch (Affiliation: Leibniz Inst. for Solid State & Mater. Res., Dresden, Germany), S. Scheinert
Journal: IEEE Trans. Electron Devices (USA), vol.52, no.1, p.47-55 (Jan. 2005)
Publisher: IEEE, USA
Language: English
ISSN: 0018-9383, Full text
Document type: Journal article
Abstract: Recently, Shannon and Gerstner introduced thesource-gated thin-film transistor (SGT) with undoped a-Si:H asthe active layer, claiming that it overcomes some fundamentallimitations of the field-effect transistor. In the common thin-filmtransistors, the channel is controlled by the gate and thecurrent saturates when the drain end of the channel becomesdepleted due to the drain voltage. For this operation, thechannel contacts to source and drain must be ohmic. Bycontrast, in the SGT, source has a depletion (Schottky)contact to the film and it is situated on the film surfaceopposite to the channel. This device is rather similar to thetop-contact (TOC) organic field-effect transistor (OFET) withSchottky-type contacts which has been investigated by us. Wesimulated the SGT and found that indeed the operation isessentially the same as that one of the Schottky-contact TOCOFET, and it differs from the verbal description given byShannon and Gerstner. We found that, apart from the unusualvoltage dependencies of the current with an abrupt transitioninto saturation at lower drain voltage, the main feature of theSGT is a strongly reduced current due to the series resistanceof the depleted region between source and channel. The SGTenables indeed higher voltage gain at lower voltages.However, a reduced transconductance and large source-gateoverlap capacitance lead to a reduced cut-off frequency. Also,a reduction of the on-current may be limited by requirementson the on-off ratio (24 refs.)
Inspec No.: 8249842
169 Nanoscale FinFETs with gate-source/drain underlap
Author(s): V. Trivedi, J.G. Fossum, M.M. Chowdhury (Affiliation: Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA)
Journal: IEEE Trans. Electron Devices (USA), vol.52, no.1, p.56-62 (Jan. 2005)
Publisher: IEEE, USA
Language: English
ISSN: 0018-9383, Full text
Document type: Journal article
Abstract: Using two-dimensional numerical device simulations,we show that optimally designed nanoscale FinFETs withundoped bodies require gate-source/drain (G-S/D) underlapthat can be effectively achieved via large, doable straggle inthe S-D fin-extension doping profile without causing S-Dpunch-through. The effective underlap significantly relaxes thefin-thickness requirement for control of short-channel effects(SCEs) via a bias-dependent effective channel length (Leff),which is long in weak inversion and approaches the gatelength in strong inversion. Dependence of Leff on the S/Ddoping profile defines a design tradeoff regarding SCEs andS/D series resistance that can be optimized, depending on thefin width, via engineering of the doping profile in the S/D finextensions.The noted optimization is exemplified via a welltemperedFinFET design with an 18-nm gate length, showingfurther that designs with effective underlap yield minimalparasitic capacitance and reduce leakage components suchas gate-induced drain leakage current (21 refs.)
Inspec No.: 8249843
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