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170 Impacts of nonrectangular fin cross section on the electrical characteristics of FinFET
Author(s): Xusheng Wu, P.C.H. Chan, M. Chan (Affiliation: Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China)
Journal: IEEE Trans. Electron Devices (USA), vol.52, no.1, p.63-8 (Jan. 2005)
Publisher: IEEE, USA
Language: English
ISSN: 0018-9383, Full text
Document type: Journal article
Abstract: The effects of nonrectangular fin cross section ofdouble-gate FinFETs are studied. For a given top-fin width,which is defined by the photolithography step, the shortchanneleffect immunity is degraded by the inclination of thesidewalls. The nonrectangular fin geometry also leads tononuniform current flow and current crowding in the verticaldirection. Together with the nonuniform series resistancealong the height of the fin, a nonlinear dependence of oncurrentwith fin heights (which have been regarded as the Wsin planar MOSFET) is observed. The impacts of nonverticalsidewall have been characterized according to the inclinationangle in this work. Under different inclination angles asdictated by the processing technology, the deviceperformances at various fin heights are characterized. A newdesign constraint that limits the choice of fin height for a giventechnology is also discussed (18 refs.)
Inspec No.: 8249844
171 Impact ionization MOS (I-MOS)-Part I: device and circuit simulations
Author(s): K. Gopalakrishnan, P.B. Griffin, J.D. Plummer (Affiliation: Stanford Univ., CA, USA)
Journal: IEEE Trans. Electron Devices (USA), vol.52, no.1, p.69-76 (Jan. 2005)
Publisher: IEEE, USA
Language: English
ISSN: 0018-9383, Full text
Document type: Journal article
Abstract: One of the fundamental problems in the continuedscaling of transistors is the 60 mV/dec room temperature limitin the subthreshold slope. In part I this work, a novel transistorbased on the field-effect control of impact-ionization (I-MOS) isexplored through detailed device and circuit simulations. TheI-MOS uses gated-modulation of the breakdown voltage of ap-i-n diode to switch from the OFF state to the ON state andvice-versa. Device simulations using MEDICI show that the IMOShas a subthreshold slope of 5 mV/dec or lower andION>1 mA/ìm at 400 K. Simulations were used to furtherexplore the characteristics of the I-MOS including thetransients of the turn-on mechanism, the short-channel effect,scalability, and other important device attributes. Circuit modesimulations were also used to explore circuit design using IMOSdevices and the design of an I-MOS inverter. Thesesimulations indicated that the I-MOS has the potential toreplace CMOS in high performance and low power digitalapplications. Part II of this work focuses on I-MOSexperimental results with emphasis on hot carrier effects,germanium p-i-n data and breakdown in recessed structuredevices (32 refs.)
Inspec No.: 8249845
172 Impact ionization MOS (I-MOS)-Part II: experimental results
Author(s): K. Gopalakrishnan, R. Woo, C. Jungemann, P.B. Griffin, J.D. Plummer (Affiliation: Stanford Univ., CA, USA)
Journal: IEEE Trans. Electron Devices (USA), vol.52, no.1, p.77-84 (Jan. 2005)
Publisher: IEEE, USA
Language: English
ISSN: 0018-9383, Full text
Document type: Journal article
Abstract: Part I of this paper dealt with the fundamentalunderstanding of device physics and circuit design in a noveltransistor, based on the field-effect control of impact-ionization(I-MOS). This paper focuses on experimental results obtainedon various silicon-based prototypes of the I-MOS. Thefabricated p-channel I-MOS devices showed extremely abrupttransitions from the OFF state to the ON state with asubthreshold slope of less than 10 mV/dec at 300 K. Thesefirst experimental prototypes of the I-MOS also showedsignificant hot carrier effects resulting in threshold voltageshifts and degradation of subthreshold slope with repeatedmeasurements. Hot carrier damage was seen to be muchworse in nMOS devices than in pMOS devices. Monte Carlosimulations revealed that the hot carrier damage was causedby holes (electrons) underneath the gate in pMOS (nMOS)devices and, thus, consequently explained the difference inhot carrier effects in p-channel versus n-channel I-MOStransistors. Recessed channel devices were also explored tounderstand the effects of surfaces on the enhancement in thebreakdown voltage in I-MOS devices. In order to reduce thebreakdown voltage needed for device operation, simple p-i-ndevices were fabricated in germanium. These devices showedmuch lower values of breakdown voltage and excellentmatches to MEDICI simulations (22 refs.)
Inspec No.: 8249846
173 Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs
Author(s): Chunshan Yin, P.C.H. Chan (Affiliation: Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China)
Journal: IEEE Trans. Electron Devices (USA), vol.52, no.1, p.85-90 (Jan. 2005)
Publisher: IEEE, USA
Language: English
ISSN: 0018-9383, Full text
Document type: Journal article
Abstract: A planar double-gate SOI MOSFET (DG-SOI) withthin channel and thick source/drain (S/D) was successfullyfabricated. Using both experimental data and simulationresults, the S/D asymmetric effect induced by gatemisalignment was studied. For a misaligned DG-SOI, there isgate nonoverlapped region on one side and extra gateoverlapped region on the other side. The nonoverlappedregion introduces extra series resistance and weaklycontrolled channel, while the extra overlapped regionintroduces additional overlap capacitance and gate leakagecurrent. We compared two cases: bottom gate shift to sourceside (DG_S) and bottom gate shift to drain side (DG_D). At thesame gate misalignment value, DG_S resulted in a largerdrain-induced barrier lowering effect and smaller overlapcapacitance at drain side than DG_D. Because of reduceddrain-side capacitance, the speed of three-stage ring oscillatorof DG_S, with 20% gate misalignment length (Lmis) over gatelength (Lg), or Lmis/Lg=20%, was faster than that of two-gatealigned DG-SOI (17 refs.)
Inspec No.: 8249847
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