HTE Labs - 174 Correct biasing rules for virtual DG mode operation in SOI-MOSFETs 175 A new low-power pMOS poly-Si inverter for AMDs 176 Positive bias temperature instability effects of Hfbased nMOSFETs with various nitrogen and silicon profiles 177 Design and process development of ion sensitive FET's 178 DC analysis of circuits containing short-channel MOS transistors 179 Low dissipation current photocoupler for gate drive

174 Correct biasing rules for virtual DG mode operation in SOI-MOSFETs Author(s): A. Ohata (Affiliation: IMEP ENSERG, Grenoble, France ), J. Pretet, S. Cristoloveanu, A. Zaslavsky Journal: IEEE Trans. Electron Devices (USA), vol.52, no.1, p.124-5 (Jan. 2005) Publisher: IEEE, USA Language: English ISSN: 0018-9383, Full text Document type: Journal article Abstract: The appropriate biasing rules for virtual double-gate(DG) operation of silicon-on-insulator (SOI)-MOSFETs areinvestigated. The cause for the optimistic subthreshold swing,achieved by the conventional biasing rule, is discussed and acorrect methodology is proposed. Furthermore, we select theproper threshold voltages for the virtual DG operation basedon the condition that both interfaces are simultaneouslyinverted (6 refs.) Inspec No.: 8249854 175 A new low-power pMOS poly-Si inverter for AMDs Author(s): Sang-Hoon Jung, Woo-Jin Nam, Jae-Hoon Lee, Jae-Hong Jeon, Min-Koo Han (Affiliation: Sch. of Electr. Eng., Seoul Nat. Univ., South Korea) Journal: IEEE Electron Device Lett. (USA), vol.26, no.1, p.23-5 (Jan. 2005) Publisher: IEEE, USA Language: English ISSN: 0741-3106, Full text Document type: Journal article Abstract: A new low-power inverter using only p-type poly-Sithin-film transistors for the driving circuits of active matrixliquid crystal displays and active matrix organic light-emittingdiodes is proposed and fabricated. The proposed pMOSinverter using capacitive coupling and bootstrappingsuccessfully eliminated the troublesome through current andexhibited a wide output swing from VDD to VSS withoutadditional signals (7 refs.) Inspec No.: 8250020 176 Positive bias temperature instability effects of Hfbased nMOSFETs with various nitrogen and silicon profiles Author(s): Changhwan Choi, Chang-Seok Kang, Chang Yong Kang, Se Jong Rhee, M.S. Akbar, S.A. Krishnan, Manhong Zhang, J.C. Lee (Affiliation: Dept. of Electr. & Comput. Eng., Univ. of Texas, Austin, TX, USA) Journal: IEEE Electron Device Lett. (USA), vol.26, no.1, p.32-4 (Jan. 2005) Publisher: IEEE, USA Language: English ISSN: 0741-3106, Full text Document type: Journal article Abstract: Positive bias temperature instability (PBTI) effects ofHfO2 -based nMOSFETs with various nitrogen profiles in HfO2were investigated. The nitrogen profile was modulated by aninserting Si layer (~6â) into hafnium oxynitride gate dielectrics.The Si layer is used to trap nitrogen and to suppress nitrogenout-diffusion during subsequent anneals. Compared to controlHfOxNy without Si insertion, the Si-inserted HfOxNy samplesexhibited reduced PBTI degradation, especially if the Si layerwas placed further from the Si interface. The improvement canbe attributed to the reduction of oxide bulk trapped as well asreduced interface trapped charge generation resulting fromcompensation effect of inserted Si layer (16 refs.) Inspec No.: 8250023 177 Design and process development of ion sensitive FET's Author(s): B. Jaroszewicz, D. Tomaszewski, A. Kociubinski, M. Nikodem, P. Grabiec (Affiliation: Inst. Technol. Elektronowej, Warszawa, Poland), D. Pijanowska, W. Torbicz, M. Chudy Journal: Elektronika (Poland), vol.45, no.10, p.27-8 (2004) Publisher: SIGMA NOT, Poland Language: Polish ISSN: 0033-2089 Document type: Journal article Abstract: Two ISFETs designs have been presented in thispaper. In the first design called front side contact ISFET, thetransistor source (S), drain (D) electrodes and the gate havebeen placed on the front side of the structure. In the secondone called back side contact ISFET, the electrodes S and Dhave been placed on the opposite side to the front surfacewith the gate functioning as a chemically sensitive area. Theassembled devices have been characterised electrically andtested in the solutions of different pH (5 refs.) Inspec No.: 8248412 178 DC analysis of circuits containing short-channel MOS transistors Author(s): M. Tadeusiewicz, S. Halgas (Affiliation: Wydzial Elektrotechniki i Elektroniki, Politechnika Lodzka, Lodz, Poland) Journal: Elektronika (Poland), vol.45, no.11, p.30-3 (2004) Publisher: SIGMA NOT, Poland Language: Polish ISSN: 0033-2089 Document type: Journal article Abstract: Circuits containing short-channel MOS transistors,having multiple DC solutions, are analyzed in this paper. Thebasic question how to find efficiently all the DC solutions andinput-output characteristics are considered. A two-partprocedure is described for computing all the DC solutions.This procedure exploits the nth power law model of MOStransistors and the algorithm of successive contraction,division and elimination to find preliminary solutions, and nextthe BSIM model to correct them using controlled SPICEsimulations (32 refs.) Inspec No.: 8248422 179 Low dissipation current photocoupler for gate drive Author(s): H. Morikawa, Y. Masuda, T. Murata Journal: Sharp Tech. J. (Japan), no.89, p.87-90 (Aug. 2004) Publisher: Sharp Co, Japan Language: Japanese ISSN: 0285-0362 Document type: Journal article Inspec No.: 8249747

	Semiconductor Devices - Miscellaneous articles, abstracts, technical notes, letters, publications
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PAPER INFORMATION	PAPER INFORMATION
174 Correct biasing rules for virtual DG mode operation in SOI-MOSFETs Author(s): A. Ohata (Affiliation: IMEP ENSERG, Grenoble, France ), J. Pretet, S. Cristoloveanu, A. Zaslavsky Journal: IEEE Trans. Electron Devices (USA), vol.52, no.1, p.124-5 (Jan. 2005) Publisher: IEEE, USA Language: English ISSN: 0018-9383, Full text Document type: Journal article Abstract: The appropriate biasing rules for virtual double-gate(DG) operation of silicon-on-insulator (SOI)-MOSFETs areinvestigated. The cause for the optimistic subthreshold swing,achieved by the conventional biasing rule, is discussed and acorrect methodology is proposed. Furthermore, we select theproper threshold voltages for the virtual DG operation basedon the condition that both interfaces are simultaneouslyinverted (6 refs.) Inspec No.: 8249854	175 A new low-power pMOS poly-Si inverter for AMDs Author(s): Sang-Hoon Jung, Woo-Jin Nam, Jae-Hoon Lee, Jae-Hong Jeon, Min-Koo Han (Affiliation: Sch. of Electr. Eng., Seoul Nat. Univ., South Korea) Journal: IEEE Electron Device Lett. (USA), vol.26, no.1, p.23-5 (Jan. 2005) Publisher: IEEE, USA Language: English ISSN: 0741-3106, Full text Document type: Journal article Abstract: A new low-power inverter using only p-type poly-Sithin-film transistors for the driving circuits of active matrixliquid crystal displays and active matrix organic light-emittingdiodes is proposed and fabricated. The proposed pMOSinverter using capacitive coupling and bootstrappingsuccessfully eliminated the troublesome through current andexhibited a wide output swing from VDD to VSS withoutadditional signals (7 refs.) Inspec No.: 8250020
176 Positive bias temperature instability effects of Hfbased nMOSFETs with various nitrogen and silicon profiles Author(s): Changhwan Choi, Chang-Seok Kang, Chang Yong Kang, Se Jong Rhee, M.S. Akbar, S.A. Krishnan, Manhong Zhang, J.C. Lee (Affiliation: Dept. of Electr. & Comput. Eng., Univ. of Texas, Austin, TX, USA) Journal: IEEE Electron Device Lett. (USA), vol.26, no.1, p.32-4 (Jan. 2005) Publisher: IEEE, USA Language: English ISSN: 0741-3106, Full text Document type: Journal article Abstract: Positive bias temperature instability (PBTI) effects ofHfO2 -based nMOSFETs with various nitrogen profiles in HfO2were investigated. The nitrogen profile was modulated by aninserting Si layer (~6â) into hafnium oxynitride gate dielectrics.The Si layer is used to trap nitrogen and to suppress nitrogenout-diffusion during subsequent anneals. Compared to controlHfOxNy without Si insertion, the Si-inserted HfOxNy samplesexhibited reduced PBTI degradation, especially if the Si layerwas placed further from the Si interface. The improvement canbe attributed to the reduction of oxide bulk trapped as well asreduced interface trapped charge generation resulting fromcompensation effect of inserted Si layer (16 refs.) Inspec No.: 8250023	177 Design and process development of ion sensitive FET's Author(s): B. Jaroszewicz, D. Tomaszewski, A. Kociubinski, M. Nikodem, P. Grabiec (Affiliation: Inst. Technol. Elektronowej, Warszawa, Poland), D. Pijanowska, W. Torbicz, M. Chudy Journal: Elektronika (Poland), vol.45, no.10, p.27-8 (2004) Publisher: SIGMA NOT, Poland Language: Polish ISSN: 0033-2089 Document type: Journal article Abstract: Two ISFETs designs have been presented in thispaper. In the first design called front side contact ISFET, thetransistor source (S), drain (D) electrodes and the gate havebeen placed on the front side of the structure. In the secondone called back side contact ISFET, the electrodes S and Dhave been placed on the opposite side to the front surfacewith the gate functioning as a chemically sensitive area. Theassembled devices have been characterised electrically andtested in the solutions of different pH (5 refs.) Inspec No.: 8248412
178 DC analysis of circuits containing short-channel MOS transistors Author(s): M. Tadeusiewicz, S. Halgas (Affiliation: Wydzial Elektrotechniki i Elektroniki, Politechnika Lodzka, Lodz, Poland) Journal: Elektronika (Poland), vol.45, no.11, p.30-3 (2004) Publisher: SIGMA NOT, Poland Language: Polish ISSN: 0033-2089 Document type: Journal article Abstract: Circuits containing short-channel MOS transistors,having multiple DC solutions, are analyzed in this paper. Thebasic question how to find efficiently all the DC solutions andinput-output characteristics are considered. A two-partprocedure is described for computing all the DC solutions.This procedure exploits the nth power law model of MOStransistors and the algorithm of successive contraction,division and elimination to find preliminary solutions, and nextthe BSIM model to correct them using controlled SPICEsimulations (32 refs.) Inspec No.: 8248422	179 Low dissipation current photocoupler for gate drive Author(s): H. Morikawa, Y. Masuda, T. Murata Journal: Sharp Tech. J. (Japan), no.89, p.87-90 (Aug. 2004) Publisher: Sharp Co, Japan Language: Japanese ISSN: 0285-0362 Document type: Journal article Inspec No.: 8249747

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