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34 Results of radiation effects on a chalcogenide non-volatile memory array
Author(s): J. Maimon (Affiliation: Ovonyx Inc., Manassas, VA, USA ), K. Hunt, J. Rodgers, L. Burcin, K. Knowles
Conference: 2004 IEEE Aerospace Conference Proceedings, Big Sky, MT, USA
Conference Date: 6-13 March 2004
Sponsor(s): Aerosp. and Electron. Syst. Soc Publication: 2004 IEEE Aerospace Conference Proceedings (IEEE Cat. No.04TH8720)
Publisher: IEEE, USA, 2004
Language: English
ISBN: 0 7803 8155 6 Page: 2306-15 Vol.4
Document type: Conference paper
Abstract: We report on the progress of a recent addition to non-volatile solid state memory technologies suited for space and other ionizing radiation environments. We summarize the material and processing science behind the current generation of chalcogenide phase-change memories fabricated on CMOS structures. The chalcogenide material used for phase-change applications in rewritable optical storage (Ge2Sb2Te5) has been integrated with a radiation hardened CMOS process to produce 64 kbit memory arrays. On selected arrays electrical testing demonstrated up to 100% memory cell yield, 100 ns programming and read speeds, and write currents as low as 1 mA/bit. Devices functioned normally from -55°C to 125°C. Write/read endurance has been demonstrated to 1×108 before first bit failure. Radiation results show no degradation to the hardened CMOS or effects that can be attributed to the phasechange material. Future applications of the technology are discussed (21 refs.)
Inspec No.: 8255589
35 A reconfigurable computing board for high performance processing in space
Author(s): D. Van Buren, P. Murray, T. Langley (Affiliation: SEAKR Eng. Inc., Centennial, CO, USA)
Conference: 2004 IEEE Aerospace Conference Proceedings, Big Sky, MT, USA
Conference Date: 6-13 March 2004
Sponsor(s): Aerosp. and Electron. Syst. Soc
Publication: 2004 IEEE Aerospace Conference Proceedings (IEEE Cat. No.04TH8720)
Publisher: IEEE, USA, 2004
Language: English
ISBN: 0 7803 8155 6 Page: 2316-26 Vol.4
Document type: Conference paper
Abstract: There is a tremendous need for space-qualified highperformance processing hardware. This need is being driven by increased sensor data rates in systems with limited downlink capacity, and a desire for autonomous operation. Traditional processing elements such as ASICs and sequential processors are less than ideal for high-performance processing. SRAM-based FPGAs offer the highest processing performance available in a flexible, reprogrammable, and low risk space-qualified device. However, the use of SRAM-based FPGAs in space applications can also be challenging. This paper discusses the design of FPGA-based reconfigurable computing (RCC) hardware for space. It discusses the processing capability of the given architecture, and gives performance metrics for typical applications. Radiation effect mitigation techniques are discussed, and upset rates are given for different levels of mitigation. Finally, the development cycle for typical applications is addressed, including an overview of the tools that are available to implement processing algorithms and upset mitigation techniques (14 refs.)
Inspec No.: 8255590
36 SPICE macro models for annular MOSFETs
Author(s): K. Strohbehn, M.N. Martin (Affiliation: Appl. Phys. Lab., Johns Hopkins Univ., Laurel, MD, USA)
Conference: 2004 IEEE Aerospace Conference Proceedings, Big Sky, MT, USA
Conference Date: 6-13 March 2004
Sponsor(s): Aerosp. and Electron. Syst. Soc
Publication: 2004 IEEE Aerospace Conference Proceedings (IEEE Cat. No.04TH8720)
Publisher: IEEE, USA, 2004
Language: English
ISBN: 0 7803 8155 6 Page: 2370-7 Vol.4
Document type: Conference paper
Abstract: MOSFETs with annular, or enclosed, geometries are now finding frequent use in rad-hard by design (RHBD) approaches to designing custom CMOS ASICs for aerospace applications. Unfortunately, these devices are not accurately modeled by the BSIM3 models normally provided for devices with ordinary rectangular gates. We present a SPICE macro model for an annular n-channel MOSFET to account for the annular geometry effects on gate overlap capacitance and output conductance (5 refs.)
Inspec No.: 8255595
37 RADAR - reconfigurable analog and digital array for radiation-hardened circuits
Author(s): L. McMurchie, C. Sechen (Affiliation: Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA)
Conference: 2004 IEEE Aerospace Conference Proceedings, Big Sky, MT, USA
Conference Date: 6-13 March 2004
Sponsor(s): Aerosp. and Electron. Syst. Soc
Publication: 2004 IEEE Aerospace Conference Proceedings (IEEE Cat. No.04TH8720)
Publisher: IEEE, USA, 2004
Language: English
ISBN: 0 7803 8155 6 Page: 2417-26 Vol.4
Document type: Conference paper
Abstract: Because of their flexibility and reprogrammability, FPGAs have been proposed for many uses in avionics. Existing commercial FPGAs, being finegrained, are programmable at the bit level, allowing them to be used across a wide range of applications. Compared to an ASIC developed for a specific application, however, such a finegrained FPGA consumes more power and exhibits higher latency and/or lower throughput. In this paper, we describe RADAR - a coarse-grained, programmable, radiationhardened array that exhibits power and throughput similar to ASICs, yet contains a high degree of programmability. Containing multipliers, adders, SRAMs and a programmable interconnect, RADAR is customized to the DSP domain and targets applications that require low power and high throughput. The degree of radiation hardening in RADAR is a programmable feature, allowing a tradeoff between radiation hardness, throughput, and power (12 refs.)
Inspec No.: 8255600
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